# Clock constraints
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_clock -name "sys_clk" -period 20ns [get_ports {osc_clk}] -waveform {0.000ns 10.000ns}
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
set_clock_groups -exclusive -group {altera_reserved_tck}

Info: Linking frontEndOS.elf
nios2-elf-g++  -T'../frontEndOS_bsp/linker.x' -msys-crt0='../frontEndOS_bsp/obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../frontEndOS_bsp   -Wl,-Map=frontEndOS.map   -O0 -g -Wall   -EL -mno-hw-div -mhw-mul -mno-hw-mulx  -o frontEndOS.elf obj/Buffer.o obj/KeeperDevices.o obj/Spi.o obj/devices/Device.o obj/devices/FM25CL64.o obj/devices/Register.o obj/devices/deviceInfo.o obj/init.o obj/main.o obj/timer.o obj/uart.o -lm
nios2-elf-insert frontEndOS.elf --thread_model ucosii --cpu_name cpu_0 --simulation_enabled false --id 0 --sidp 0x1004158 --timestamp 1297768557 --stderr_dev uart_0 --stdin_dev uart_0 --stdout_dev terminal --sopc_system_name cpuNew --quartus_project_dir "D:/Work/Quartus/TestBench" --jdi D:/Work/Quartus/TestBench/software/frontEndOS_bsp/../../topLevel.jdi
Info: (frontEndOS.elf) 211 KBytes program size (code + initialized data).
Info:                  7973 KBytes free for stack + heap.
Info: Creating frontEndOS.objdump
nios2-elf-objdump --disassemble --syms --all-header --source frontEndOS.elf >frontEndOS.objdump
[frontEndOS build complete]

#**************************************************************
# sdram clocks (from PLL)
#**************************************************************
set main_clk pll1_inst|altpll_component|auto_generated|pll1|clk[0]
set sdram_clk pll1_inst|altpll_component|auto_generated|pll1|clk[1]
create_generated_clock -name sdram_clk_pin -source $sdram_clk

set_clock_groups -exclusive -group [list $main_clk $sdram_clk sdram_clk_pin]
#**************************************************************
# sdram timings
#**************************************************************
set tAC 5.4
set tOH 3
set tCM_Hold 0.8
set tCM_Setup 1.5
set tD_Hold 0.8
set tD_Setup 1.5
set tA_Hold 0.8
set tA_Setup 1.5
#**************************************************************
# Board Timings
set CLK_BD_MAX 0.1
set CLK_BD_MIN - 0.1
set DATA_BD_MAX 0.1
set DATA_BD_MIN - 0.1
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -max -clock sdram_clk_pin [expr $CLK_BD_MAX + $tAC + $DATA_BD_MAX] [get_ports {sdram_dq[*]}]
set_input_delay -min -clock sdram_clk_pin [expr $CLK_BD_MIN + $tOH + $DATA_BD_MIN] [get_ports {sdram_dq[*]}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -max -clock sdram_clk_pin [expr $DATA_BD_MAX + $tD_Setup - $CLK_BD_MIN] [get_ports {sdram_dq[*]}]
set_output_delay -min -clock sdram_clk_pin [expr $DATA_BD_MIN + $tD_Hold - $CLK_BD_MAX] [get_ports {sdram_dq[*]}]
set_output_delay -max -clock sdram_clk_pin [expr $DATA_BD_MAX + $tCM_Setup - $CLK_BD_MIN] [get_ports {sdram_cas_n sdram_ras_n sdram_we_n sdram_cs_n sdram_cke sdram_dqm[*]}]
set_output_delay -min -clock sdram_clk_pin [expr $DATA_BD_MIN + $tCM_Hold - $CLK_BD_MAX] [get_ports {sdram_cas_n sdram_ras_n sdram_we_n sdram_cs_n sdram_cke sdram_dqm[*]}]
set_output_delay -max -clock sdram_clk_pin [expr $DATA_BD_MAX + $tA_Setup - $CLK_BD_MIN] [get_ports {sdram_addr[*] sdram_ba[*]}]
set_output_delay -min -clock sdram_clk_pin [expr $DATA_BD_MIN + $tA_Hold - $CLK_BD_MAX] [get_ports {sdram_addr[*] sdram_ba[*]}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_clocks {sdram_clk_pin}] -to [get_clocks $main_clk] -setup -end 2
set_multicycle_path -from [get_clocks {sdram_clk_pin}] -to [get_clocks $main_clk] -hold -end 0

# TCL File Generated by Component Editor 10.1
# Wed Mar 02 13:46:07 YEKT 2011
# DO NOT MODIFY


# +-----------------------------------
# |
# | DAC_memOut "DAC_memOut" v1.0
# | Anisimov 2011.03.02.13:46:07
# |
# |
# +-----------------------------------

# +-----------------------------------
# | request TCL package from ACDS 10.1
# |
package require -exact sopc 10.1
# |
# +-----------------------------------

# +-----------------------------------
# | module DAC_memOut
# |
set_module_property NAME DAC_memOut
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Memories and Memory Controllers/SDRAM"
set_module_property AUTHOR Juvf
set_module_property DISPLAY_NAME DAC_memOut
set_module_property INSTANTIATE_IN_SYSTEM_MODULE false
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
# |
# +-----------------------------------

# +-----------------------------------
# | files
# |
# |
# +-----------------------------------

# +-----------------------------------
# | parameters
# |
# |
# +-----------------------------------

# +-----------------------------------
# | display items
# |
# |
# +-----------------------------------

# +-----------------------------------
# | connection point avalon_tristate_slave
# |
add_interface avalon_tristate_slave avalon_tristate end
set_interface_property avalon_tristate_slave activeCSThroughReadLatency false
set_interface_property avalon_tristate_slave associatedClock clock
set_interface_property avalon_tristate_slave explicitAddressSpan 0
set_interface_property avalon_tristate_slave holdTime 0
set_interface_property avalon_tristate_slave isMemoryDevice true
set_interface_property avalon_tristate_slave isNonVolatileStorage false
set_interface_property avalon_tristate_slave maximumPendingReadTransactions 0
set_interface_property avalon_tristate_slave printableDevice false
set_interface_property avalon_tristate_slave readLatency 0
set_interface_property avalon_tristate_slave readWaitStates 0
set_interface_property avalon_tristate_slave readWaitTime 0
set_interface_property avalon_tristate_slave setupTime 0
set_interface_property avalon_tristate_slave timingUnits Cycles
set_interface_property avalon_tristate_slave writeWaitTime 0

set_interface_property avalon_tristate_slave ENABLED true

add_interface_port avalon_tristate_slave addr address Input 10
add_interface_port avalon_tristate_slave data data Bidir 16
add_interface_port avalon_tristate_slave rd read Input 1
add_interface_port avalon_tristate_slave wr write Input 1
add_interface_port avalon_tristate_slave cs chipselect_n Input 1
# |
# +-----------------------------------

# +-----------------------------------
# | connection point clock
# |
add_interface clock clock end
set_interface_property clock clockRate 0

set_interface_property clock ENABLED true

add_interface_port clock clk clk Input 1
# |
# +-----------------------------------