__attribute__ ((section (".dac"),used)) unsigned int dacData[512];
....
while(1)
{
dacData[16] = 0x55aa;
pauseMm(1000);
}

__attribute__ ((section (".myPio "),used)) unsigned int led;
...
//а потом писать в порт
led = 0x12;

static int fdterm; // FILEDESCRIPTOR RETURNED BY OPEN
..
fdterm = open("/dev/uart1", O_RDWR | O_NONBLOCK | O_NOCTTY | O_SYNC);
..


reading is done by

..
res=read(fdterm,uart1_tempbuff,sizeof(uart1_tempbu ff)-1);
if(res>0) {
... we have received some bytes
}

typedef struct flash_region
{
  int   offset;
  int   region_size;
  int   number_of_blocks;
  int   block_size;
}flash_region;

#include <stdio.h>
#include "alt_types.h"
#include "system.h"
#include <io.h>
#include <sys/alt_flash.h>
#include <unistd.h>
int main()
{
flash_region* regions;
alt_flash_fd* fd;
int number_of_regions;
int ret_code;
int i;
printf("Hello from Nios II!\n");
fd = alt_flash_open_dev(CFI_FLASH_0_NAME);
if (fd)
{
ret_code = alt_get_flash_info(fd, &regions, &number_of_regions);
for (i=0;i<number_of_regions;i++)
{
printf("Offset: %d\r\n", regions[i].offset);
printf("Region Size: %d\r\n", regions[i].region_size);
printf("Number of Blocks: %d\r\n", regions[i].number_of_blocks);
printf("Block Size: %d\r\n\r\n", regions[i].block_size);
}
}
}

Resetting and pausing target processor: OK
Found CFI table in 16 bit mode
Raw CFI query table read from device:
0: 89 00 1B 88 01 00 01 00 89 00 CF BF 01 00 01 00 ................
10: 89 00 1B 88 01 00 01 00 89 00 CF BF 01 00 01 00 ................
20: 51 00 52 00 59 00 01 00 00 00 0A 00 01 00 00 00 Q.R.Y...........
30: 00 00 00 00 00 00 17 00 20 00 85 00 95 00 08 00 ........ .......
40: 09 00 0A 00 00 00 01 00 01 00 02 00 00 00 18 00 ................
CFI query table read from device:
10: 51 52 59 01 00 0A 01 00 00 00 00 17 20 85 95 08 QRY......... ...
20: 09 0A 00 01 01 02 00 18 01 00 06 00 02 03 00 80 ................
30: 00 7E 00 00 02 00 00 00 00 FF FF FF FF FF FF FF .~..............
40: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
50: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
60: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
70: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
CFI extended table read from device:
0: 50 52 49 31 34 E6 01 00 00 01 03 00 18 90 02 80 PRI14...........
10: 00 03 03 89 00 00 00 00 00 00 10 00 04 03 04 01 ................
Read autoselect code 0089-881B (in 16 bit mode)
No CFI override data for [FLASH-0089-881B]
Target timeout loop runs 1497780 times/s
Timeout set to 767 loops
Device size is 16MByte
Erase regions are:
offset 0: 4 x 32K
offset 20000: 127 x 128K
Device supports Intel style programming algorithm
Multi-byte programming with 64 byte buffer
Sector erase timeout is 4s
Word program timeout is 512us
Buffer program timeout is 1ms
Leaving target processor paused

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity PC104 is
    port (
        ats_s0_address      : in    std_logic_vector(15 downto 0):=(others => 'Z');      
        ats_s0_read_n       : in    std_logic                     := '1';                              
        ats_s0_data         : inout std_logic_vector(15 downto 0) := (others => 'Z');
        ats_s0_chipselect_n : in    std_logic                     := '1';                          
        ats_s0_write_n      : in    std_logic                     := '1';                          
            
        clk                 : in    std_logic                     := '1';                            
        reset               : in    std_logic                     := '1';                            
        
        
        
        cos_RD_n            : out    std_logic                    := '1';  
        cos_WR_n            : out    std_logic                    := '1';
        cos_CS_n            : out    std_logic                    := '1';
    --    cos_data_ISA : inout std_logic_vector(15 downto 0) := (others => 'Z');
        cos_ADDR_ISA          : out std_logic_vector(15 downto 0) := (others => '0')
        

        
    );
end entity PC104;

architecture rtl of PC104 is
begin

    cos_RD_n<=ats_s0_read_n;
    cos_WR_n<=ats_s0_write_n;
    cos_CS_n<=ats_s0_chipselect_n;
    
    cos_ADDR_ISA<=ats_s0_address;
    
    --cos_data_ISA<=ats_s0_data when ats_s0_write_n='0' else (others => 'Z');
    --ats_s0_data<=cos_data_ISA when ats_s0_read_n='0' else (others => 'Z');

end architecture rtl; -- of new_component