**** Build of configuration Debug for project simple_socket_server_0 ****

make -s all includes
Creating generated_app.mk...
      3 [main] ? (4072) C:\altera\11.0\quartus\bin\cygwin\bin\make.exe: *** fatal error - couldn't allocate heap, Win32 error 487, base 0x800000, top 0x890000, reserve_size 585728, allocsize 589824, page_const 4096
      2 [main] make 2808 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0x100, errno 11
make: C:/altera/11.0/nios2eds/components/altera_hal/build/app_rules.mk:147: fork: Resource temporarily unavailable
/bin/sh: /cygdrive/c/altera/11.0/nios2eds/components/altera_hal: is a directory
      3 [main] ? (3668) C:\altera\11.0\quartus\bin\cygwin\bin\sh.exe: *** fatal error - couldn't allocate heap, Win32 error 487, base 0x680000, top 0x690000, reserve_size 61440, allocsize 65536, page_const 4096
      2 [main] sh 2916 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0x100, errno 11
/bin/sh: fork: Resource temporarily unavailable
Error: no processor component available.
SOPC_BUILDER_PATH may be incorrectly set in your environment.
      4 [main] ? (3688) C:\altera\11.0\quartus\bin\cygwin\bin\make.exe: *** fatal error - couldn't allocate heap, Win32 error 487, base 0x6C0000, top 0x7A0000, reserve_size 913408, allocsize 917504, page_const 4096
      2 [main] make 2496 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0x100, errno 11
make[1]: vfork: Resource temporarily unavailable
Creating system.h...
      4 [main] ? (3472) C:\altera\11.0\quartus\bin\cygwin\bin\sh.exe: *** fatal error - couldn't allocate heap, Win32 error 487, base 0x710000, top 0x720000, reserve_size 61440, allocsize 65536, page_const 4096
      2 [main] sh 3104 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0x100, errno 11
/cygdrive/c/altera/11.0/nios2eds/bin/gtf-generate: fork: Resource temporarily unavailable
make[1]: *** [system_description/../obj/system.h-t] Error 128
make: *** [system_project] Error 2
Build completed in 113.863 seconds;

**** Build of configuration Debug for project hello_world_0 ****

make -s all includes
      4 [main] ? (2940) C:\altera\11.0\quartus\bin\cygwin\bin\sh.exe: *** fatal error - couldn't allocate heap, Win32 error 487, base 0x6D0000, top 0x6E0000, reserve_size 61440, allocsize 65536, page_const 4096
      2 [main] sh 3004 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0x100, errno 11
/bin/sh: fork: Resource temporarily unavailable
Creating generated_app.mk...
Creating generated_all.mk...
Error: no processor component available.
SOPC_BUILDER_PATH may be incorrectly set in your environment.

make[1]: *** [proc_check] Error 1
make: *** [system_project] Error 2
Build completed in 157.968 seconds
;

InterNiche Portable TCP/IP, v3.1
=============== Software License Reminder ================
This software project uses an unlicensed version of the NicheStack TCP/IP
Network Stack - Nios II Edition. If you want to ship resulting object
code in your product, you must purchase a license for this software from
Altera. For information go to: "http://www.altera.com/nichestack"
=====================================================
InterNiche Portable TCP/IP, v3.1

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.
Your Ethernet MAC address is 00:07:ed:ff:aa:20
prepped 1 interface, initializing...
Created "Inet main" task (Prio: 2)
Created "clock tick" task (Prio: 3)
smsc91c111 Auto-negotiation: 100 Mbps, Full Duplex
SMSC ethernet Rev: 0x3392, ram: 8192
mctest init called
IP address of et1 : 192.168.1.234
DHCP timed out, going back to default IP address(es)
Created "web server" task (Prio: 4)

Web Server starting up

#include <stdio.h>
#include "system.h"
#include "io.h"
#include "alt_types.h"
#include "sys/alt_irq.h"
#include "altera_avalon_uart_regs.h"

void* context;

alt_8 a = 255;
void uart_test(); // прототип ф-ци выполняемой в прерывании

int main()
{
IOWR(LED_BASE, 0, a);
IOWR(UART_BASE, 3, 128); // маска преерывания
alt_irq_register (UART_IRQ, context, (void*)uart_test); // здесь говорим компилятору неоходимое о прерывании
IOWR(UART_BASE, 4, 5208); // скорость передачи задана в SOPCBUILDER'е, но ещё раз напомним
    
while(1)
    {    
      IOWR(LED_BASE, 0, a);
    }
}


void uart_test() // прерывание
  {
      a = IORD(UART_BASE, 0) & 255; читаем принятый байт
      IOWR(UART_BASE, 4, 2000); // изменяем скорость передачи
      IOWR(UART_BASE, 1, a); // предаём принятый байт на внешн. устр. с другой скоростью
      IOWR(UART_BASE, 4, 5208); // возвращаем предыдущую скорость (9600 бод/сек)
      return;
  }

void uart_test()
  {
      a = IORD(UART_BASE, 0) & 255;
      IOWR(UART_BASE, 4, 2000);
      IOWR(UART_BASE, 1, a);
      alt_32 i = 0;
      for(i = 0; i < 10000; i++)
      {}
      IOWR(UART_BASE, 4, 5208);
      return;
  }

#include "altera_avalon_fifo_regs.h"
#include "altera_avalon_fifo_util.h"
#include "system.h"
#include "sys/alt_irq.h"
#include <stdio.h>
#include <stdlib.h>
#include "altera_avalon_pio_regs.h"
#include "system.h"
#include <stdio.h>




int main()
{ alt_u32 tmp;
tmp = 100;
// чтение регистра статуса
printf("LEVEL = %u\n", altera_avalon_fifo_read_level(FIFO_IN_CSR_BASE) );
printf("STATUS = %u\n", altera_avalon_fifo_read_status(FIFO_IN_CSR_BASE,
ALTERA_AVALON_FIFO_STATUS_ALL) );
printf("EVENT = %u\n", altera_avalon_fifo_read_event(FIFO_IN_CSR_BASE,
ALTERA_AVALON_FIFO_EVENT_ALL) );
//altera_avalon_fifo_write_ienable(FIFO_IN_CSR_BASE, 3);
printf("IENABLE = %u\n", altera_avalon_fifo_read_ienable(FIFO_IN_CSR_BASE,
ALTERA_AVALON_FIFO_IENABLE_ALL) );
printf("ALMOSTEMPTY = %u\n",
altera_avalon_fifo_read_almostempty(FIFO_IN_CSR_BASE) );
printf("ALMOSTFULL = %u\n\n",
altera_avalon_fifo_read_almostfull(FIFO_IN_CSR_BASE));

// запись в FIFO
altera_avalon_write_fifo( 10 , FIFO_IN_CSR_BASE, tmp);


  return 0;
}

alt_u32 tmp, tmp_read;
tmp = 0xff;

// запись в FIFO
altera_avalon_fifo_write_fifo( FIFO_IN_BASE, FIFO_IN_CSR_BASE, tmp);

// чтение из FIFO

tmp_read = altera_avalon_fifo_read_fifo(FIFO_OUT_BASE, FIFO_IN_CSR_BASE);

printf("read = %02x\n", tmp_read);

/*
* fifo_in configuration
*
*/

#define ALT_MODULE_CLASS_fifo_in altera_avalon_fifo
#define FIFO_IN_AVALONMM_AVALONMM_DATA_WIDTH 32
#define FIFO_IN_AVALONMM_AVALONST_DATA_WIDTH 32
#define FIFO_IN_BASE 0x1108c
#define FIFO_IN_BITS_PER_SYMBOL 16
#define FIFO_IN_CHANNEL_WIDTH 8
#define FIFO_IN_ERROR_WIDTH 8
#define FIFO_IN_FIFO_DEPTH 16
#define FIFO_IN_IRQ -1
#define FIFO_IN_IRQ_INTERRUPT_CONTROLLER_ID -1
#define FIFO_IN_NAME "/dev/fifo_in"
#define FIFO_IN_SINGLE_CLOCK_MODE 1
#define FIFO_IN_SPAN 4
#define FIFO_IN_SYMBOLS_PER_BEAT 2
#define FIFO_IN_TYPE "altera_avalon_fifo"
#define FIFO_IN_USE_AVALONMM_READ_SLAVE 1
#define FIFO_IN_USE_AVALONMM_WRITE_SLAVE 1
#define FIFO_IN_USE_AVALONST_SINK 0
#define FIFO_IN_USE_AVALONST_SOURCE 0
#define FIFO_IN_USE_BACKPRESSURE 1
#define FIFO_IN_USE_IRQ 1
#define FIFO_IN_USE_PACKET 1
#define FIFO_IN_USE_READ_CONTROL 0
#define FIFO_IN_USE_REGISTER 0
#define FIFO_IN_USE_WRITE_CONTROL 1


/*
* fifo_in_csr configuration
*
*/

#define ALT_MODULE_CLASS_fifo_in_csr altera_avalon_fifo
#define FIFO_IN_CSR_AVALONMM_AVALONMM_DATA_WIDTH 32
#define FIFO_IN_CSR_AVALONMM_AVALONST_DATA_WIDTH 32
#define FIFO_IN_CSR_BASE 0x11040
#define FIFO_IN_CSR_BITS_PER_SYMBOL 16
#define FIFO_IN_CSR_CHANNEL_WIDTH 8
#define FIFO_IN_CSR_ERROR_WIDTH 8
#define FIFO_IN_CSR_FIFO_DEPTH 16
#define FIFO_IN_CSR_IRQ 10
#define FIFO_IN_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
#define FIFO_IN_CSR_NAME "/dev/fifo_in_csr"
#define FIFO_IN_CSR_SINGLE_CLOCK_MODE 1
#define FIFO_IN_CSR_SPAN 32
#define FIFO_IN_CSR_SYMBOLS_PER_BEAT 2
#define FIFO_IN_CSR_TYPE "altera_avalon_fifo"
#define FIFO_IN_CSR_USE_AVALONMM_READ_SLAVE 1
#define FIFO_IN_CSR_USE_AVALONMM_WRITE_SLAVE 1
#define FIFO_IN_CSR_USE_AVALONST_SINK 0
#define FIFO_IN_CSR_USE_AVALONST_SOURCE 0
#define FIFO_IN_CSR_USE_BACKPRESSURE 1
#define FIFO_IN_CSR_USE_IRQ 1
#define FIFO_IN_CSR_USE_PACKET 1
#define FIFO_IN_CSR_USE_READ_CONTROL 0
#define FIFO_IN_CSR_USE_REGISTER 0
#define FIFO_IN_CSR_USE_WRITE_CONTROL 1


/*
* fifo_out configuration
*
*/

#define ALT_MODULE_CLASS_fifo_out altera_avalon_fifo
#define FIFO_OUT_AVALONMM_AVALONMM_DATA_WIDTH 32
#define FIFO_OUT_AVALONMM_AVALONST_DATA_WIDTH 32
#define FIFO_OUT_BASE 0x11088
#define FIFO_OUT_BITS_PER_SYMBOL 16
#define FIFO_OUT_CHANNEL_WIDTH 8
#define FIFO_OUT_ERROR_WIDTH 8
#define FIFO_OUT_FIFO_DEPTH 16
#define FIFO_OUT_IRQ -1
#define FIFO_OUT_IRQ_INTERRUPT_CONTROLLER_ID -1
#define FIFO_OUT_NAME "/dev/fifo_out"
#define FIFO_OUT_SINGLE_CLOCK_MODE 1
#define FIFO_OUT_SPAN 4
#define FIFO_OUT_SYMBOLS_PER_BEAT 2
#define FIFO_OUT_TYPE "altera_avalon_fifo"
#define FIFO_OUT_USE_AVALONMM_READ_SLAVE 1
#define FIFO_OUT_USE_AVALONMM_WRITE_SLAVE 1
#define FIFO_OUT_USE_AVALONST_SINK 0
#define FIFO_OUT_USE_AVALONST_SOURCE 0
#define FIFO_OUT_USE_BACKPRESSURE 1
#define FIFO_OUT_USE_IRQ 1
#define FIFO_OUT_USE_PACKET 1
#define FIFO_OUT_USE_READ_CONTROL 0
#define FIFO_OUT_USE_REGISTER 0
#define FIFO_OUT_USE_WRITE_CONTROL 1

alt_u32 tmp, tmp_read;
tmp = 0xff;

// запись
    altera_avalon_fifo_write_fifo( FIFO_IN_USE_AVALONMM_WRITE_SLAVE, FIFO_IN_CSR_BASE, tmp);
// чтение    
    tmp_read = altera_avalon_fifo_read_fifo(FIFO_IN_USE_AVALONMM_READ_SLAVE , FIFO_IN_CSR_BASE);
    printf("read = %02x\n", tmp_read);