class TCritSect
{
public:
    TCritSect () : StatusReg(__get_interrupt_state()) { __disable_interrupt(); }
     ~TCritSect() { __set_interrupt_state(StatusReg); }
private:
     TStatusReg StatusReg;
};

        INLINE byte GetCount() const { TCritSect cs; return count; }

     mrs    r3, PRIMASK    
      cpsid    i          
      msr    PRIMASK, r3    
      ldrb    r0, [r0, #8]
      bx    lr

     mrs    r3, PRIMASK    
      cpsid    i          
      ldrb    r0, [r0, #6]
      msr    PRIMASK, r3    
      bx    lr

return count;

return Cbuf.get_count();

byte get_count() const { return count; }
...
volatile byte count;

INLINE inline void __set_interrupt_state(TStatusReg status)
{
    __asm__ __volatile__ (
        "MSR PRIMASK, %0\n"
        : : "r"(status)
    );
}

extern unsigned char const k[8][16];

typedef union
{
struct
{
unsigned y0: 4;
unsigned y1: 4;
unsigned y2: 4;
unsigned y3: 4;
unsigned y4: 4;
unsigned y5: 4;
unsigned y6: 4;
unsigned y7: 4;
} y;
unsigned int x;
} var;

unsigned int func( var v )
{
v.y.y0 = k[0][v.y.y0];
v.y.y1 = k[1][v.y.y1];
v.y.y2 = k[2][v.y.y2];
v.y.y3 = k[3][v.y.y3];
v.y.y4 = k[4][v.y.y4];
v.y.y5 = k[5][v.y.y5];
v.y.y6 = k[6][v.y.y6];
v.y.y7 = k[7][v.y.y7];
return v.x;
}

20 func:
24 0000 1A4B ldr r3, .L3
25 0002 00F00F02 and r2, r0, #15
26 0006 9A5C ldrb r2, [r3, r2] @ zero_extendqisi2
27 0008 62F30300 bfi r0, r2, #0, #4
28 000c C0F30312 ubfx r2, r0, #4, #4
29 0010 9A18 adds r2, r3, r2
30 0012 127C ldrb r2, [r2, #16] @ zero_extendqisi2
31 0014 62F30710 bfi r0, r2, #4, #4
32 0018 C0F30322 ubfx r2, r0, #8, #4
33 001c 9A18 adds r2, r3, r2
34 001e 92F82020 ldrb r2, [r2, #32] @ zero_extendqisi2
35 0022 62F30B20 bfi r0, r2, #8, #4
36 0026 C0F30332 ubfx r2, r0, #12, #4
37 002a 9A18 adds r2, r3, r2
38 002c 92F83020 ldrb r2, [r2, #48] @ zero_extendqisi2
39 0030 62F30F30 bfi r0, r2, #12, #4
40 0034 C0F30342 ubfx r2, r0, #16, #4
41 0038 9A18 adds r2, r3, r2
42 003a 92F84020 ldrb r2, [r2, #64] @ zero_extendqisi2
43 003e 62F31340 bfi r0, r2, #16, #4
44 0042 C0F30352 ubfx r2, r0, #20, #4
45 0046 9A18 adds r2, r3, r2
46 0048 92F85020 ldrb r2, [r2, #80] @ zero_extendqisi2
47 004c 62F31750 bfi r0, r2, #20, #4
48 0050 C0F30362 ubfx r2, r0, #24, #4
49 0054 9A18 adds r2, r3, r2
50 0056 92F86020 ldrb r2, [r2, #96] @ zero_extendqisi2
51 005a 62F31B60 bfi r0, r2, #24, #4
52 005e 03EB1073 add r3, r3, r0, lsr #28
53 0062 93F87030 ldrb r3, [r3, #112] @ zero_extendqisi2
54 0066 63F31F70 bfi r0, r3, #28, #4
55 006a 7047 bx lr

10 func:
13 0000 F3B5 push {r0, r1, r4, r5, r6, r7, lr}
14 0002 1E4B ldr r3, .L2
15 0004 00F00F0C and ip, r0, #15
16 0008 C0F30311 ubfx r1, r0, #4, #4
17 000c 13F80C60 ldrb r6, [r3, ip] @ zero_extendqisi2
18 0010 5918 adds r1, r3, r1
19 0012 C0F30322 ubfx r2, r0, #8, #4
20 0016 91F810C0 ldrb ip, [r1, #16] @ zero_extendqisi2
21 001a 9A18 adds r2, r3, r2
22 001c C0F30351 ubfx r1, r0, #20, #4
23 0020 C0F30335 ubfx r5, r0, #12, #4
24 0024 C0F30344 ubfx r4, r0, #16, #4
25 0028 1C19 adds r4, r3, r4
26 002a 0091 str r1, [sp, #0]
27 002c C0F30367 ubfx r7, r0, #24, #4
28 0030 03EB1071 add r1, r3, r0, lsr #28
29 0034 92F82020 ldrb r2, [r2, #32] @ zero_extendqisi2
30 0038 5D19 adds r5, r3, r5
31 003a 66F30300 bfi r0, r6, #0, #4
32 003e 95F83050 ldrb r5, [r5, #48] @ zero_extendqisi2
33 0042 6CF30710 bfi r0, ip, #4, #4
34 0046 94F840C0 ldrb ip, [r4, #64] @ zero_extendqisi2
35 004a 009C ldr r4, [sp, #0]
36 004c 62F30B20 bfi r0, r2, #8, #4
37 0050 0191 str r1, [sp, #4]
38 0052 65F30F30 bfi r0, r5, #12, #4
39 0056 1919 adds r1, r3, r4
40 0058 91F85020 ldrb r2, [r1, #80] @ zero_extendqisi2
41 005c DB19 adds r3, r3, r7
42 005e 6CF31340 bfi r0, ip, #16, #4
43 0062 DDF804C0 ldr ip, [sp, #4]
44 0066 93F86010 ldrb r1, [r3, #96] @ zero_extendqisi2
45 006a 62F31750 bfi r0, r2, #20, #4
46 006e 9CF87030 ldrb r3, [ip, #112] @ zero_extendqisi2
47 0072 61F31B60 bfi r0, r1, #24, #4
48 0076 63F31F70 bfi r0, r3, #28, #4
49 007a FCBD pop {r2, r3, r4, r5, r6, r7, pc}

unsigned int func( var v )
{
var vv;

vv.y.y0 = k[0][v.y.y0];
vv.y.y1 = k[1][v.y.y1];
vv.y.y2 = k[2][v.y.y2];
vv.y.y3 = k[3][v.y.y3];
vv.y.y4 = k[4][v.y.y4];
vv.y.y5 = k[5][v.y.y5];
vv.y.y6 = k[6][v.y.y6];
vv.y.y7 = k[7][v.y.y7];
return vv.x;
}

# For most CPUs we have an assembly soft-float implementations.
# However this is not true for ARMv6M.  Here we want to use the soft-fp C
# implementation.  The soft-fp code is only build for ARMv6M.  This pulls
# in the asm implementation for other CPUs.
LIB1ASMFUNCS += _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func \
    _call_via_rX _interwork_call_via_rX \
    _lshrdi3 _ashrdi3 _ashldi3 \
    _arm_negdf2 _arm_addsubdf3 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \
    _arm_fixdfsi _arm_fixunsdfsi \
    _arm_truncdfsf2 _arm_negsf2 _arm_addsubsf3 _arm_muldivsf3 \
    _arm_cmpsf2 _arm_unordsf2 _arm_fixsfsi _arm_fixunssfsi \
    _arm_floatdidf _arm_floatdisf _arm_floatundidf _arm_floatundisf \
    _clzsi2 _clzdi2

MULTILIB_OPTIONS     = marm/mthumb
MULTILIB_DIRNAMES    = arm thumb
MULTILIB_EXCEPTIONS  =
MULTILIB_MATCHES     =

MULTILIB_OPTIONS      += march=armv7
MULTILIB_DIRNAMES     += armv7
MULTILIB_EXCEPTIONS   += march=armv7* marm/*march=armv7*
MULTILIB_MATCHES      += march?armv7=march?armv7-a
MULTILIB_MATCHES      += march?armv7=march?armv7-r
MULTILIB_MATCHES      += march?armv7=march?armv7-m
MULTILIB_MATCHES      += march?armv7=mcpu?cortex-a8
MULTILIB_MATCHES      += march?armv7=mcpu?cortex-r4

MULTILIB_OPTIONS      += mcpu=cortex-m3
MULTILIB_DIRNAMES     += cortex-m3
MULTILIB_EXCEPTIONS   += mcpu=cortex-m3* *march=armv7*/mcpu=cortex-m3*  marm/*mcpu=cortex-m3*
MULTILIB_MATCHES      += mcpu?cortex-m3=mtune?cortex-m3


# Not quite true.  We can support hard-vfp calling in Thumb2, but how do we
# express that here?  Also, we really need architecture v5e or later
# (mcrr etc).
#MULTILIB_OPTIONS       += mfloat-abi=hard
#MULTILIB_DIRNAMES      += fpu
#MULTILIB_EXCEPTIONS    += *mthumb/*mfloat-abi=hard*

# MULTILIB_OPTIONS    += mcpu=ep9312
# MULTILIB_DIRNAMES   += ep9312
# MULTILIB_EXCEPTIONS += *mthumb/*mcpu=ep9312*
#     
#MULTILIB_OPTIONS     += mlittle-endian/mbig-endian
#MULTILIB_DIRNAMES    += le be
#MULTILIB_MATCHES     += mbig-endian=mbe mlittle-endian=mle
#
#MULTILIB_OPTIONS    += mhard-float/msoft-float
#MULTILIB_DIRNAMES   += fpu soft
#MULTILIB_EXCEPTIONS += *mthumb/*mhard-float*
#
MULTILIB_OPTIONS    += mno-thumb-interwork/mthumb-interwork
MULTILIB_DIRNAMES   += normal interwork
#
# MULTILIB_OPTIONS    += fno-leading-underscore/fleading-underscore
# MULTILIB_DIRNAMES   += elf under
#
# MULTILIB_OPTIONS    += mcpu=arm7
# MULTILIB_DIRNAMES   += nofmult
# MULTILIB_EXCEPTIONS += *mthumb*/*mcpu=arm7*
# # Note: the multilib_exceptions matches both -mthumb and
# # -mthumb-interwork
# #
# # We have to match all the arm cpu variants which do not have the
# # multiply instruction and treat them as if the user had specified
# # -mcpu=arm7.  Note that in the following the ? is interpreted as
# # an = for the purposes of matching command line options.
# # FIXME: There ought to be a better way to do this.
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm7d
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm7di
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm70
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm700
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm700i
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm710
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm710c
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm7100
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm7500
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm7500fe
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm6
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm60
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm600
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm610
# MULTILIB_MATCHES    += mcpu?arm7=mcpu?arm620

EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o

# If EXTRA_MULTILIB_PARTS is not defined above then define EXTRA_PARTS here
# EXTRA_PARTS = crtbegin.o crtend.o crti.o crtn.o

LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib

# Currently there is a bug somewhere in GCC's alias analysis
# or scheduling code that is breaking _fpmul_parts in fp-bit.c.
# Disabling function inlining is a workaround for this problem.
TARGET_LIBGCC2_CFLAGS = -fno-inline

# Assemble startup files.
$(T)crti.o: $(srcdir)/config/arm/crti.asm $(GCC_PASSES)
    $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
    -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/arm/crti.asm

$(T)crtn.o: $(srcdir)/config/arm/crtn.asm $(GCC_PASSES)
    $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
    -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/arm/crtn.asm