Errata The revision letter in this section refers to the revision of the AT90CAN128 device.
Rev A & B - Rev A (Part marked M128CAN11-EL)
- Rev B (Part marked 90CAN128-EL)
• Sporadic CAN error frames
• Spike on TWI pins when TWI is enabled
• ADC differential gain error with x1 & x10 amplification
• Asynchronous Timer-2 wakes up without interrupt
• SPI programming timing
• IDCODE masks data from TDI input
6. Sporadic CAN error frames
When BRP = 0 the CAN controller may desynchronize and send one error frame to ask
for the retransmission of the incoming frame, even though it had no error.
This is likely to occur with BRP = 0 after long inter frame periods without synchronization
(low bus load). The CAN macro can still properly synchronize on frames following the
error.
Problem Fix/Workaround
Set BRP greater than 0 in CANBT1
5. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
Problem Fix/Workaround
No known workaround, enable AT90CAN128 TWI first versus the others nodes of
the TWI network.
4. ADC differential gain error with x1 & x10 amplification
Gain error of - 4 lsb has been characterized on the part.
Problem Fix/Workaround
Software adjustment.
3. Asynchronous Timer-2 wakes up without interrupt
The asynchronous timer can wake from sleep without giving interrupt. The error only
occurs if the interrupt flag(s) is cleared by software less than 4 cycles before going
to sleep and this clear is done exactly when it is supposed to be set (compare match
or overflow). Only the interrupts flags are affected by the clear, not the signal witch
is used to wake up the part.
Problem Fix/Workaround
No known workaround, try to lock the code to avoid such a timing.
2. SPI programming timing
When the fuse high byte or the extended fuse byte has been written, it is necessary
to wait the end of the programming using “Poll RDY/BSY” instruction. If this instruc384
AT90CAN128
4250D–CAN–07/04
tion is entered too speedily after the “Write Fuse” instruction, the fuse low byte is
written instead of high fuse /extended fuse byte.
Problem Fix/Workaround
Wait sometime before applying the “Poll RDY/BSY” instruction. For 8MHz system
clock, waiting 1 μs is sufficient.
1. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices
are replaced by all-ones during Update-DR.
Problem Fix / Workaround
– If AT90CAN128 is the only device in the scan chain, the problem is not
visible.
– Select the Device ID Register of the AT90CAN128 by issuing the IDCODE
instruction or by entering the Test-Logic-Reset state of the TAP controller to
read out the contents of its Device ID Register and possibly data from
succeeding devices of the scan chain. Issue the BYPASS instruction to the
AT90CAN128 while reading the Device ID Registers of preceding devices of
the boundary scan chain.
– If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the AT90CAN128 must be the first device in the chain.